1. Field of the Invention
The present invention relates, in general, to semiconductor devices and a method of fabricating semiconductor devices and, more particularly, to a method of reducing stain difference of a passivation layer after a pad is formed.
2. Background of the Invention
A semiconductor device is a kind of a circuit device in which conductive, nonconductive, and semiconductor films may be formed on a semiconductor substrate and then processed to form electronic and electrical elements and wirings. As the degree of integration of semiconductor devices increases, a width of a wiring and an element becomes very small. Thus, the semiconductor device becomes very complex, calling for precise control of conditions for a formation process thereof.
To achieve high integration of semiconductor devices, the size of elements and wirings is continually decreasing. In order to form lots of elements in a limited area, a multi-layer structure may-be used. Further, to connect elements and wirings and to connect upper and lower wirings, holes may be formed in a pre-metal dielectric (PMD) layer and then filled with conductive material to form contacts.
Terminals may be formed in the semiconductor device for connecting circuits in a lower substrate, comprising various elements and wirings, to external circuits and to other upper substrate structures.
A terminal, i.e. a pad, may be formed from metal, such as aluminum (Al), as part of a metal line. A semiconductor device in which pads are formed may be covered with a passivation layer over all so as to prevent external shock and/or the introduction of moisture, oxygen and so on. The passivation layer may also prevent the influence of a molding compound, applied in a subsequent packaging step, on the semiconductor device packaged inside the molding compound.
The passivation layer may be formed by using an oxide layer, such as high density plasma-undoped silicate glass (HDP-USG), or a silicon nitride layer, which may be deposited by a chemical vapor deposition (CVD) method employing high-density plasma. The layers can have a single layer structure or a multi-layered structure in which the oxide layer and the silicon nitride layer are alternately deposited.
As the degree of integration of semiconductor devices increases, a space between top metal patterns also tends to become narrower. In particular, high density memory products often have a great difference in the degree of integration. For example, some memory products are divided into a memory region with a high degree of integration and a logic region with a low degree of integration. Accordingly, among other adverse effects associated with a higher degree of integration of top metal patterns, a stain difference may occur in a passivation layer when regions having a low degree of integration are also present.
In general, the passivation layer may have a thickness of about 12000 angstrom or higher. It is also inevitable that there is some stain difference due to equipment if the passivation layer is deposited by a CVD method. However, voids are generated because a deposited insulating (i.e., passivation) layer often does not completely fill all of the increasingly narrower spaces between metal patterns. Such stain difference becomes more profound due to these voids.
It is understood that in certain applications this stain difference phenomenon does not have a great influence on the external quality of semiconductor products, but can be considered as a failure in terms of external appearance. In products using capacitors, however, this phenomenon should preferably be eliminated because it may have an effect on a capacitor's coupling ratio.